The present invention relates generally to mixed-signal integrated circuits, and particularly to nonvolatile programmable digital potentiometers.
Nonvolatile programmable digital potentiometers, known also as nonvolatile reprogrammable electronic potentiometers or digitally controlled potentiometers, have been, for about the last 15 years, some of the most emerging front-line integrated circuits (ICs). They are used in LCD (Liquid Crystal Display) screen adjustment, volume control, automated product calibration, remote adjustment of equipment, signal processing, and other applications requiring the replacement of mechanical potentiometers.
FIG. 1 illustrates an embodiment of a nonvolatile reprogrammable potentiometer 10, as it is described in U.S. Pat. No. 4,668,932, the disclosure of which is hereby incorporated by reference. The potentiometer 10 includes a series chain of impedance elements 40 and additional circuitry for accessing the chain. The chain 40 has a first element 13, a last element 15, and one or more intermediate elements 12. The first element 13 is connected to a first terminal 14 (called high impedance terminal or H in other references), and the last element 15 to a second terminal 16 (called low impedance terminal or L in other references). A plurality 44 of electrically controllable switches 20 connects every internal node (or tap) of the chain 40, to a third terminal 18 (called wiper terminal or W in other references). An output line 36 from a selecting block 38 controls each switch 20; the block 38 determines which electrically controllable switch 20 is closed at a given time. The selecting block 38 consists of a counter 24 connected to a decoder 22. The state of the counter may be incremented or decremented by signals on counter input terminals 28 and 30. The terminal 28 is used to apply count increment signal INCR, and the terminal 30 to apply an up/down control select signal UP/DN SEL. Storage block 60 stores the status of the counter 24 in response to a preselected signal. The storage block 60 consists of a nonvolatile memory 25, a control circuitry 26, and a circuitry 27 used to detect the status of the counter 24. The chip select line CHIP SEL 33 and the control line 32 are used to control when the memory 25 is updated and when it updates the counter 24, the control line 32 being connected to the supply voltage of the circuit.
Prior-art digital potentiometers, such as the potentiometer 10 of FIG. 1, tend to produce errors when operated as voltage dividers having a low impedance load connected to the third or wiper terminal 18.
In general, the present invention provides a digital potentiometer, configurable and programmable using nonvolatile memory. Additional current flows through the upper part of a conventional digital potentiometer resistor chain, if an output load is connected to ground, or through the lower part of the resistor chain, if the load is connected to supply voltage. This additional current tends to cause errors in conventional digital potentiometers when operated as voltage dividers having a low impedance load connected to a wiper terminal thereof. In order to avoid this phenomenon, one aspect of the present invention provides an output buffer, connected between an internal wiper terminal and an output terminal.
In one embodiment, a digital potentiometer includes first, second, and third signal terminals and a chain of series-connected impedance elements with multiple tap points and having endpoints connected to the first and second signal terminals. First switching devices are respectively connected to the multiple tap points and to an internal wiper node. A configurable output stage is connected between the internal wiper node and the third signal terminal and comprises: a rail-to-rail operational amplifier in unity-gain configuration, a bias circuitry, and a second switching device. The operational amplifier is connected in parallel with the second switching device. The bias circuitry and the second switching device are controlled by a configuration signal such that the operational amplifier is biased only if the second switching device is turned-off. A selecting block indicating an identity of a turned-on one of the first switching devices is also provided and is controlled by external and internal digital signals. A nonvolatile memory and control block for storage of the identity of the turned-on one of the first switching devices, and for the storage of a status of the configuration signal, the nonvolatile memory and control block is also controlled by external and internal digital signals.
This way, in certain applications, it is possible to take advantage of the low output resistance given by the analog buffer. Because certain applications need the removal of the buffer, the operational amplifier can be shutdown and bypassed by the second switching device, used in turned-on state, obtaining a behavior similar to the digital potentiometers without an output buffer.
Another aspect of the present invention improves overall reliability, by enhancing the writing procedure of the nonvolatile memory, which may comprise an EEPROM. Using a dual-writing circuitry, first complemented data, then the data itself, are written in the EEPROM nonvolatile memory, thereby improving the reliability.
Another aspect of the present invention provides an improved transient response at the output, or third, terminal, by using a Gray-code counter and decoder. The Gray-code counter has a single bit changed at one time and no decode glitch.
Make-before-break digital circuitry may be used in controlling the first switching devices such that an open one of the first switching devices must be closed before a closed one of the first switching devices opens. The make-before-break digital circuitry ensures that the internal wiper node is always connected to at least one tap of the chain.
Another aspect of the present invention provides a layout floor plan and layout designs for switches and resistor array, in order to obtain the overall performances and an improved behavior to ESD (electrostatic discharge) and short-circuited operation without the buffer.
Additional details regarding the present system and method may be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.